 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| SMH4046 Preliminary Information 1 (See Last Page) Hot-Swap, Active DC Output Control (ADOCTM) Power Manager with I2C lnterface FEATURES & APPLICATIONS * Full voltage Control for hot-swap applications - Add-in Card insertion detection - Platform voltage detection * Universal FPGA configuration I/O pins * High Voltage and logic level enable outputs * Active control (ADOCTM) for three downstream DC/DC converters with 0.5% accuracy * Margining of three DC/DC converters * Power-up sequencing of all supply voltages * Power-down sequencing in Forward or Reverse * UV and OV sensors per channel with programmable reset and interrupt * Programmable glitch filter for all channels * Configuration may be locked * Auto monitoring of all channels and Ext Temp * I2CTM serial bus interface * Programmable slew rate control * Integrated 2K EEPROM Applications * Monitor/Control Distributed and POL Supplies * Multi-voltage Processors, DSPs, ASICs used in Telecom or server systems INTRODUCTION The SMH4046 is an all-inclusive power management controller that integrates hot swap protection of three positive-voltage supplies (+12V or less). In addition to hot swapping three bus voltages, it provides sequencing and Active DC Output Control (ADOCTM) of three on-card DC-DC converters as used in blade servers and Telecom systems. It can also upload configuration code from the host to on-card FPGAs. All six channels can cascade-sequence during powerup in any order as set by either hardware or firmware; and sequence down in forward or reverse order. ADOCTM control of the three DC/DC converters maintains their accuracy to within 0.5% of the set point using an internal voltage reference. ADOCTM is also included during "margining" to allow card-by-card performance evaluation during production with arbitrary setting within 10% in any combination. A full set of monitoring and control features are included, with user programmability that can be locked. The SMH4046 uses the I2C bus interface for programming and FPGA configuration. Ejector Switch FS TYPICAL APPLICATIONS DRAWING BD_SEL1# FPGA 5 FPGA_CFGDNE FPGA_NSTS PND1# FS VMA TRIMA PUPA VCC5 VMB TRIMB PUPB VMC TRIMC PUPC VGATE5 47nF HST_RST# PND2# CARD_5V VCC3 VGATE3 VGG_CAP 1uF HEALTHY# CARD_V_VLD Temp Sensor EXT_TMP 1Vref SCL A2 SDA RESET CARD_3V VCC12 DRVREN# CARD_12V FAULT IRQ 47nF 10 270k 47nF DC/DC #1 TRIM VOUT OE VIN DC/DC #2 TRIM VOUT OE VIN TRIM OE VIN DC/DC #3 VOUT FPGA_NCFG FPGA_DCLK FPGA_DO +3.3V +5V +12V GND TEMP GND GND +5V Vout1 Vout2 BOARD CONNECTOR GND GND HST_PWR G D S PCI_RST# BD_SEL# SMH4046 D G S HEALTHY# S G D *Hot swap *ADOCTM *Pwr On/Off Board 5V *Cascade *Sequence *Monitor Board 3.3V *Margin *I2C Vout3 Board 12V BUS CONNECTOR PreCharge Circuit Switch PCI Interface ASIC Bus IRQ FAULT CARD RESET Figure 1 - Applications Schematic using the SMH4046 Controller to hot swap and actively control the output levels of three DC/DC Converters while providing power on/off, cascade sequencing and output margining. Note: This is an applications example only. Some pins, components and values are not shown. (c) SUMMIT Microelectronics, Inc. 2004 * 1717 Fox Drive * San Jose CA 95131 * Phone 408 436-9890 * FAX 408 436-9897 The Summit Web Site can be accessed by "right" or "left" mouse clicking on the link: http://www.summitmicro.com/ 2082 1.7 08/23/04 1 SMH4046 Preliminary Information VCC12 ( +6V to +14V) 5.0V 3.3V 2.0V 1.8V 1.5V RESET tDPONA tDPONB tDPONC tDPOND tDPONE tDPONF --- tPTO --- Figure 2 - Example Power Supply Cascade Sequencing and System Initialization Using the SMH4046 GENERAL DESCRIPTION The SMH4046 is a fully integrated hot swap controller intended for use on add-in cards that are hot swapped from powered-on host platforms. The SMH4046 performs a variety of tasks starting with the validation of proper card insertion and the presence of "in-spec" voltages at the host platform interface. Once the SMH4046 switches power on, it continues to monitor the back-end power to the add-in card and the host power supply. When programmed to do so, the SMH4046 immediately asserts the RESET outputs and powers-down the add-in card when the 12V, 5V or 3.3V supplies drop below a programmable UV or above an OV threshold. In addition to the power control for the add-in card, the SMH4046 provides status signals that can be employed by the host for the control of bus interface components. On-chip EEPROM memory can be used to store serial ID numbers or other pertinent information for the individual card or as general-purpose memory. The FPGA configuration-interface provides a direct interface for simplified access to the add-in card's FPGAs using the I2C interface. The SMH4046 has the ability to monitor and sequence up to six power supplies (Figure 1). The SMH4046 can monitor the 12V input and the internal and external temperature sensors. The SMH4046 has four operating modes: Power-on sequencing mode, monitor and control mode using Active DC Output Control (ADOC), supply margining mode using ADOC, and Power-off sequencing mode. Power-on sequencing can be initiated via the HST_PWR pin or through the serial interface. In this mode, the SMH4046 sequences the power supply channels on in any order by activating the PUPx, VGATE and DRVREN# outputs while monitoring the respective converter and host voltages to ensure correct cascading of the supplies. Cascadesequencing is the ability to hold off the next sequenced supply until the previous supply reaches a programmed threshold voltage (See Figure 2). A programmable sequence termination timer can be set to disable all channels if the power-on sequence stalls. During this mode, the HEALTHY# output remains inactive and the RESET output remains active. When the HEALTHY# output is true and RESET is false, that signals the end of power-on sequencing mode. Once the Power-on sequencing mode is complete, the SMH4046 enters monitor control mode. Once all supplies have sequenced on and the voltages are above the UV settings, the Active DC Output Control (ADOC), if enabled, brings the three DC-DC converter supply output voltages to their programmed nominal settings and adjusts the output voltage under all load conditions. This feature is especially useful for supplies without sense lines as the monitor VMx pins can be routed and sense variations at the load. Typical converters have 2 to 5% accuracy output voltage ratings. The Active DC Output Control feature of the SMH4046 increases the accuracy to 0.5%. Summit Microelectronics, Inc 2082 1.7 08/23/04 2 SMH4046 Preliminary Information GENERAL DESCRIPTION (CONTINUED) The device also triggers outputs by monitoring fault conditions. The 10-bit ADC cycles through all channels every 2 ms and checks the conversions against the programmed threshold limits. The results can be used to trigger the RESET, HEALTHY# and FAULT outputs as well as to trigger a power-off or a force- shutdown operation. While the SMH4046 is in monitoring mode, a serial interface command to margin the supply voltages can bring the part into margining mode. In margining mode the SMH4046 can margin the three supply voltages in any combination of nominal, high or low voltage settings using the ADOC feature, all to within 0.5%. The margin high and margin low voltage settings can range from 0.9V to the overvoltage limit of the DC-DC converters and depends on the margin range of the converters. During this mode the HEALTHY# output is always active and the RESET output is always inactive regardless of the voltage threshold limit settings and triggers. Furthermore, the triggers for power-off and force-shutdown are temporarily disabled. The power-off sequencing mode can only be entered while the SMH4046 is in the monitoring mode. It can be initiated by either bringing the HST_PWR pin inactive, through the serial interface control, or triggered by a channel exceeding its programmed thresholds. Once power-off is initiated, active DC control is disabled, and the PUP outputs are sequenced off in either the same or reverse order as power-on sequencing. Monitoring of the supply voltages continues to ensure cascading of the supplies as they turn off. The sequence termination timer can be programmed to immediately disable all channels if the power-off sequencing stalls. The RESET output remains active throughout this mode while the HEALTHY# output remains inactive. The CARD_3V and CARD_5V monitor pins are also used to detect overcurrents on the card side 3V and 5V supply. The FAULT pin is a programmable active high/low open drain fault output that is asserted by the SMH4046 when a programmed fault condition occurs on the internal/external temperature sensor. If programmed to do so, FAULT is asserted whenever an over-current condition is detected. Fault will be released at the same time that the VGATE outputs are turned back on after a reset from the host on the HST_PWR pin. Programming is accomplished by using the I2C serial bus interface. Summit Microelectronics, Inc 2082 1.7 08/23/04 3 SMH4046 Preliminary Information INTERNAL FUNCTIONAL BLOCK DIAGRAM VGG_CAP V C C 12 V C C 5 V C C 3 1V R E F H S T_ PW R P D N 2# P D N 1# H S T_ R S T# FS E X T_TE M P VM A AD C _C AP A VM B AD C _C AP B VM C AD C _C AP C C AR D _3V C AR D _5V C AR D _12V PUPA Intern al Supp ly VR EF C o ntrol Lo gic PUPB U VL O 10-B it AD C C ascade Sequ en ce C o ntro l PUPC V G ATE 3 V G ATE 5 Tem p eratu re Sensor DRVREN# H E ALTH Y# IR Q O utpu t C o ntro l RESET C AR D _V _V LD TR IM A TR IM _C AP A FAU LT FP G A_N S TS TR IM B TR IM _C AP B TR IM C TR IM _C AP C FILTE R _C AP GND FP G A_C G FD O N E FP G A_N C FG FP G A_D O FP G A_D C LK A2 SCL SDA Active DC O u tpu t C o ntrol I/O Interface, E EP R O M M em o ry an d L im it R eg isters Figure 3 - Internal Functional Block Diagram Summit Microelectronics, Inc 2082 1.7 08/23/04 4 SMH4046 Preliminary Information PIN DESCRIPTIONS Symbol SCL A2 HST_RST Pin 1 2 3 Type I I I The I2C serial bus clock. An external address bit for I2C. Host reset. This input is the reset signal from the host interface. Asserting this pin causes a reset sequence to be performed on the card. Programmable polarity. Host power-up enable. This input provides the host system with active control over the sequencing of the power up operation. When de-asserted, the SMH4046 holds the add-in card in reset and blocks all power to the back-end logic. When HST_PWR is asserted, the power sequencing begins immediately and the reset output is driven active after the time tPURST. Programmable polarity. Force Shutdown. This programmable active high/low input is used to immediately turn off all converter enable signals and external FETs. This input can be used to sense a voltage generated from an external temperature monitoring device. Active low Interrupt output. Generated by the SMH4046 on an error condition. This signal can be used by external logic to interrupt the host. RESET is a programmable active high/low open drain output that is asserted by the SMH4046 when a programmed reset condition occurs. FAULT is a programmable active high/low open drain fault output that is asserted by the SMH4046 when a programmed fault condition occurs. Healthy is a programmable active high/low open drain output that is asserted by the SMH4046 when all programmed healthy conditions are met. Ground. Pin detect 1 is an active low CMOS level input. In conjunction with PND2#, this signal indicates proper card insertion when taken low. This pin must be connected to ground on the host side of the connector. PND1# and PND2# should be placed on opposite corners of the connector and will preferably be staggered shorter than the power connector pins. Board insertion is assumed when PND1# and PND2# are low. Pin detect 2 is an active low CMOS level input. In conjunction with PND1#, this signal indicates proper card insertion when taken low. This pin must be connected to ground on the host side of the connector. PND1# and PND2# should be placed on opposite corners of the connector and will preferably be staggered shorter than the power connector pins. Board insertion is assumed when PND1# and PND2# are low. Card voltage valid. This open drain output indicates that the card side voltages are at or above their respective trip levels. Active high. Positive converter sense line for DC/DC converter A Output voltage used to control the output of DC/DC converter A. External sample and hold capacitor input used to set the voltage on the TRIMA pin. Description HST_PWR 4 I FS EXT_TEMP IRQ# RESET (RST) FAULT HEALTHY GND 5 6 7 8 9 10 11 I I O O O O PWR PND1# 12 I PND2# 13 I CARD_V_VLD VMA TRIMA TRIM_CAPA 14 15 16 17 O I O I Summit Microelectronics, Inc 2082 1.7 08/23/04 5 SMH4046 Preliminary Information PIN DESCRIPTIONS (CONTINUED) Symbol VMB TRIMB TRIM_CAPB VMC TRIMC TRIM_CAPC 1VREF CARD_5V CARD_3V VCC3V FILT_CAP PUPC PUPB PUPA ADC_CAPC ADC_CAPB ADC_CAPA Pin 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Type I O I I O I O I I I I O O O I I I Description Positive converter sense line for DC/DC converter B Output voltage used to control the output of DC/DC converter B. External sample and hold capacitor input used to set the voltage on the TRIMB pin. Positive converter sense line for DC/DC converter C Output voltage used to control the output of DC/DC converter C. External sample and hold capacitor input used to set the voltage on the TRIMC pin. This output provides a 1V reference for pre-charging the CompactPCI bus signal pins. 5V card side supply input. This input is monitored for power integrity. If it falls below the 5V sense threshold, the CARD_V_VLD signal is de-asserted. 3.3V monitor input from the line card. This input is monitored for power integrity. If it falls below the 3.3V sense threshold, the CARD_V_VLD signal is de-asserted. 3.3V host side supply input. This input is monitored for power integrity. External capacitor input used to filter VMX inputs Programmable active high/low open drain converter enable output for DC/DC converter C. Programmable active high/low open drain converter enable output for DC/DC converter B. Programmable active high/low open drain converter enable output for DC/DC converter A. External capacitor input used to filter the VMC input to the 10-bit ADC. External capacitor input used to filter the VMB input to the 10-bit ADC. External capacitor input used to filter the VMA input to the 10-bit ADC. This pin supplies power for the high-side drivers. An external 1uF ceramic charge pump capacitor should be connected to VGG_CAP. VGG_CAP is a charge storage connection for the internal charge pump of the SMH4046. This capacitor should be of sufficient size to provide current to the VGATE outputs high side drivers under varying load conditions. For most applications this can be tied to a 1.0 F ceramic capacitor. High-side driver enable used to switch on the 12V supply. Pulldown current of 100A when on. 5V gate output. Slew rate limited high side driver output for the 5V external Power FET gate. Alternatively this can be used as a PUP output. 3.3V gate output. Slew rate limited high side driver output for the 3.3V external Power FET gate. Alternatively, this can be used as a PUP output. VGG_CAP 35 O DRVREN# VGATE5V VGATE3V 36 37 38 O O O Summit Microelectronics, Inc 2082 1.7 08/23/04 6 SMH4046 Preliminary Information PIN DESCRIPTIONS (CONTINUED) Symbol CARD_12V VCC12 VCC5V (VDD) FPGA_NSTS FPGA_CFGD ONE FPGA_NCFG FPGA_DO FPGA_DCLK NC SDA Pin 39 40 41 42 43 44 45 46 47 48 Type I I PWR I I O O O NC I/O Description 12V card side supply input. This input is monitored for power integrity. If it falls below the 12V sense threshold, the CARD_V_VLD signal is de-asserted. Bus-side 12V input This pin supplies power to the SMH4046 and is monitored for power integrity. FPGA configuration status input pin FPGA_CFGDONE indicates completion of the configuration process. FPGA_NCFG is a configuration control output. A low transition resets the target device; a low-to-high transition begins configuration. FPGA_DO provides preamble and configuration data to downstream devices in a daisy-chain. FPGA Configuration clock output. Clock output used to clock configuration data using pin FPGA_DO. No Connect The bidirectional I2C serial data line. Summit Microelectronics, Inc 2082 1.7 08/23/04 7 SMH4046 Preliminary Information PACKAGE AND PIN CONFIGURATION 48 LEAD TQFP FPGA_CFGDONE FPGA_DCLK VCC5V (VDD) FPGA_NCFG FPGA_NSTS FPGA_DO VGATE3V 38 SDA 48 47 NC 46 45 44 43 42 41 40 39 SCL A2 HST_RST HST_PWR FS EXT_TEMP IRQ# RST FAULT HEALTHY GND PND1# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 37 36 35 34 33 32 31 VGATE5V CARD12V VCC12V DRVREN# VGG_CAP ADC_CAPA ADC_CAPB ADC_CAPC PUPA PUPB PUPC FILT_CAP VCC3V CARD3V CARD5V SMH4046 30 29 28 27 26 25 TRIM_CAPA CARD_V_VLD TRIMC_CAPC TRIMA TRIM_CAPB TRIMB PND2# TRIMC VMA 1VREF VMB VMC Summit Microelectronics, Inc 2082 1.7 08/23/04 8 SMH4046 Preliminary Information ABSOLUTE MAXIMUM RATINGS Temperature Under Bias ...................... -55C to 125C Storage Temperature............................ -65C to 150C Terminal Voltage with Respect to GND: VCC3/5 Supply Voltage .....................-0.3V to 6.0V VCC12 Supply Voltage ....................-0.3V to 15.0V Open Drain Outputs..................... GND to 15.0V All Others ..............................................VDD + 0.7V Output Short Circuit Current ............................... 100mA Reflow Solder Temperature (30 secs)................. 240C Lead Solder Temperature (10 secs) ................300C Junction Temperature........................................150C ESD Rating per JEDEC.................................2000V Latch-Up testing per JEDEC........................100mA Note - The device is not guaranteed to function outside its operating rating. Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions outside those listed in the operational sections of the specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Devices are ESD sensitive. Handling precautions are recommended. RECOMMENDED OPERATING CONDITIONS Temperature Range (Industrial)...........-40C to +85C (Commercial) ..............0C to +70C VCC3V Supply Voltage................................. 2.7V to 5V VCC5V Supply Voltage................................. 2.7V to 6V VCC12V Supply Voltage... ...................6.0V to 14.0V VIN .......................................................... GND to VCC5 VOUT ...................................................... GND to 15.0V Package Thermal Resistance (JA) 48 Lead TQFP.......................................80oC/W Moisture Classification Level 1 (MSL 1) per J-STD- 020 RELIABILITY CHARACTERISTICS Data Retention.......................................100 Years Endurance.....................................100,000 Cycles DC OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND) Symbol Parameter Notes Min Typ Max Not a supply input 2.7 3.3 5.0 VCC3 Supply Voltage Monitor VCC5 VCC12 VMx IDD ITRIM Supply Voltage Supply Voltage Monitor Positive sense voltage for VMA, VMB and VMC Power Supply Current TRIMA, TRIMB, TRIMC current All TRIM pins floating TRIMx pin sourcing current TRIMx pin sinking current ITRIM 1.5mA, Depends on Trim range of DC-DC Converter VCC5V = 2.7V VCC5V = 5.0V VCC5V = 2.7V VCC5V = 5.0V ISINK = 1mA 0.2 1.5 1.5 GND 0.9xVCC5V 0.7xVCC5V Unit V V V VCC5 must be higher then any other input except VCC12 and CARD12V Not a supply input 2.7 6 -0.3 5.0 12 6.0 14 VCC5V 3 5 mA mA mA VTRIM VIH VIL VOL Margin Control and ADOC Range Input High Voltage Input Low Voltage Programmable Open Drain Outputs VCC5V VCC5V VCC5V 0.1xVCC5V 0.3xVCC5V V V V V V V Summit Microelectronics, Inc 2082 1.7 08/23/04 9 SMH4046 Preliminary Information DC OPERATING CHARACTERISTICS (CONTINUED) (Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Notes Min Typ Max VGATE VSENSE VMonitor TMonitor TSA 1VREF VREF ACC VGATE3/5 Outputs Positive Sense Voltage Monitor Threshold Step Size Temperature Threshold Step Size Internal Temperature Sensor Accuracy 1VREF Output Voltage Internal VREF Accuracy VSENSE 3.5V ADOCACC ADOC/Margin Accuracy VSENSE 3.5V VDD_CAP Rising VDD_CAP Falling -1 VM pin VM pins Internal Temp Sensor Commercial Temp Range Industrial Temp Range Optional data bus pre-charge output -3 -5 0.95 -0.4 -0.5 1.00 +0.3 5 1 +3 +5 1.05 +0.4 12 VCC5V Unit V V mV o o o C C C V % % 0.3 0.8 2.6 2.5 +0.5 +1 % V V UVLO Under Voltage Lockout Threshold1 Note 1 - (100mV typ Hysteresis) ADC characteristics N MC S/N DNL INL GAIN Offset ADC_TC IMADC Resolution Missing Codes Signal-to-Noise Ratio Differential Non-Linearity Integral Non-Linearity Positive full scale gain error Offset Error Full Scale Temperature Coefficient Analog ADC Input Impedance EXT_TEMP Minimum resolution for which no missing codes are guaranteed 10 10 72 -1/2 -1 -0.5 -1 15 10 +1/2 +1 +0.5 +1 Bits Bits db LSB LSB % LSB PPM/oC M Conversion rate = 500Hz The formula for the total ADC inaccuracy is: [((ADC read voltage) +/- INL)*(range of gain error)]+range of offset error Summit Microelectronics, Inc 2082 1.7 08/23/04 10 SMH4046 Preliminary Information AC OPERATING CHARACTERISTICS Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND. See Figure 5A and 5B Timing diagrams. Symbol Description tDOCT Programmable Over Current Trip Delay Time tDPON Programmable Power-on delay from VMX out-of-fault to PUPY active Programmable Power-off delay from VMX off to PUPY inactive Programmable Reset Time-Out Period tDPOFF tPRTO tSTT tADC tDC_CONTROL Programmable Sequence Termination Timer 10-bit ADC sampling period Active DC Control sampling period TMARGIN Margin Time from Nominal Conditions tDOCT = 5.5 s tDOCT = 8.5 s tDOCT = 11.5 s tDOCT = 14.5 s tDOCT = 17.5 s tDOCT = 20.5 s tDOCT = 23.5 s tDOCT = 26.5 s tDOCT = 29.5 s tDOCT = 32.5 s tDOCT = 35.5 s tDOCT = 38.5 s tDOCT = 41.5 s tDOCT = 44.5 s tDOCT = 47.5 s tDOCT = 50.5 s tDPON = 1 ms tDPON = 20 ms tDPON = 40 ms tDPON = 75 ms tDPOFF = 1 ms tDPOFF = 20 ms tDPOFF = 40 ms tDPOFF = 75 ms tPRTO = 1 ms tPRTO = 40 ms tPRTO = 150 ms tPRTO = 300 ms tSTT = 40 ms tSTT = 75 ms tSTT = 150 ms tSTT = 300 ms Time for ADC conversion of all 11 channels Update period for Active DC Control of channels A-C Slow Margin, + 10% change in voltage with 0.1% ripple TRIM_CAP=1F Fast Margin, + 10% change in voltage with 0.1% ripple TRIM_CAP=1F Min Typ Max Unit -15 tDOCT +15 % -15 tDPON +15 % -15 tDPOFF +15 % -15 tPRTO +15 % -15 tSTT 2 1.7 +15 % ms ms 850 ms 85 ms Summit Microelectronics, Inc 2082 1.7 08/23/04 11 SMH4046 Preliminary Information I2C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS - 100kHz Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND. See Figure 4 Timing Diagram. Conditions 100kHz Symbol Description Min Typ Max Units fSCL tLOW tHIGH tBUF tSU:STA tHD:STA tSU:STO tAA tDH tR tF tSU:DAT tHD:DAT TI tWR_CONFI G SCL Clock Frequency Clock Low Period Clock High Period Bus Free Time Start Condition Setup Time Start Condition Hold Time Stop Condition Setup Time Clock Edge to Data Valid Data Output Hold Time SCL and SDA Rise Time SCL and SDA Fall Time Data In Setup Time Data In Hold Time Noise Filter SCL and SDA Write Cycle Time Config Write Cycle Time EE Noise suppression Configuration Registers Memory Array SCL low to valid SDA (cycle n) SCL low (cycle n+1) to SDA change Note 1/ Note 1/ Before New Transmission 0 4.7 4.0 - Note 1/ 4.7 4.7 4.0 4.7 0.2 0.2 100 KHz s s s s s s 3.5 1000 300 s s ns ns ns ns 250 0 100 10 5 ns ms ms tWR_EE Note: 1/ - Guaranteed by Design. TIMING DIAGRAMS tR SCL tSU:SDA SDA (IN) tF t HD:SDA tHIGH t W R (For W rite O peration Only) t LOW tSU:DAT tSU:STO tBUF tHD:DAT tAA SDA (OUT) t DH Figure 4 - Basic I2C Serial Interface Timing Summit Microelectronics, Inc 2082 1.7 08/23/04 12 SMH4046 Preliminary Information TIMING DIAGRAMS (CONTINUED) 0 PUP A t DPONA 1 2 VM A PUP B t DPONB VM B t DPONC PUP C VM C Figure 5A - Cascade Sequencing the Supplies On and then Monitoring for Fault Conditions 2 PUP A 1 0 t DPOFFA VM A PUP B t DPOFFB VM B PUP C t DPOFFC VM C Figure 5B - Cascade Sequencing the Supplies Off Summit Microelectronics, Inc 2082 1.7 08/23/04 13 SMH4046 Preliminary Information APPLICATIONS INFORMATION Figure 6 - Typical Applications Schematic Summit Microelectronics, Inc 2082 1.7 08/23/04 14 SMH4046 Preliminary Information APPLICATIONS INFORMATION (CONTINUED) Using the schematic in Figure 6 and assuming all input voltages are within the programmed limits, application of power to the SMH4046 will enable all DC-DC converters according to the sequence programmed for each channel in the SMH4046. An I2C software Power-On command can also be used to enable the DC-DC converters. The waveforms in Figure 7 were generated using Channel 1 (12V output) for the timebase trigger. Note the outputs are asserted once the pre-programmed time limit is passed. Conversely, the SMH4046 can issue an I2C Power-Off command (Figure 8). The SMH4046 reverses the Power-Off sequence; that is, the first supply to shut off is the last to have turned on (Channel 4 in this case). As displayed in Figure 8, the supplies are turned off in reverse order of the turn-on sequence. Figure 8: SMH4046EV Sequence-Off Waveforms Tektronix TDS3054: Time/Horizontal division = 100mS Ch 1(2V/Div) = 12V output (Yellow trace) Ch 2 (1V/Div) = 1.8V DC-DC converter output (Blue trace) Ch 3 (1V/Div) = 2.5V DC-DC converter output (Purple trace) Ch 4 (1V/Div) = 5.0V output (Green trace) The SMH4046's has many features including the ability to change the channel sequence positions and slew-rates for system flexibility and software programmability to simplify changes. Figure 9 displays the SMH4046 margining the 2.5V converter high and the 1.8V converter low. Figure 7: SMH4046EV Sequence-On Waveforms Tektronix TDS3054: Time/Horizontal division = 40mS Ch 1(2V/Div) = 12V output (Yellow trace) Ch 2 (1V/Div) = 1.8V DC-DC converter output (Blue trace) Ch 3 (1V/Div) = 2.5V DC-DC converter output (Purple trace) Ch 4 (1V/Div) = 5.0V output (Green trace) Summit Microelectronics, Inc 2082 1.7 08/23/04 15 SMH4046 Preliminary Information APPLICATIONS INFORMATION (CONTINUED) COMMENTS & PRECAUTIONS The SMH4046 is a precision integrated circuit requiring certain attention is spent with regards to component selection and printed circuit board layout to ensure the greatest possible performance. Bypass all DC-DC converter outputs with a suitable low value capacitor to decrease the high frequency noise and thereby improve the SMH4046's accuracy. Locate the VCC bypass capacitors nearby the SMH4046 returning the low side directly to a ground pin on the device. Do the same for the bulk capacitor for the DC-DC converter inputs, the 3.3V and 12V inputs; if used. Add an additional low value bypass capacitor if the supplies are noisy. Figure 9: SMH4046EV Margining Waveforms Tektronix TDS3054: Time/Horizontal division = 1S Ch 1(2V/Div) = 12V output (Yellow trace) Ch 2 (1V/Div) = 1.8V DC-DC converter output (Blue trace) Ch 3 (1V/Div) = 2.5V DC-DC converter output (Purple trace) Ch 4 (1V/Div) = 5.0V output (Green trace) VCC5 Noise Noise introduced onto the supply (VCC5 pin) of the SMH4046 by the DC/DC converters or other sources may affect the ADC and ADOCtm (margining) accuracy. The result is that the ADC reading and final ADOCtm (margined) voltage may exhibit an error or the actual ADOC voltage may differ noticeably from the target value. To obtain more accurate results, an external series 20 (R47 in Figure 6) resistor should be added in series between the VCC5 pin 41 and the supply voltage and a 10F ceramic bypass capacitor (C24 in Figure 6) added from VCC5 to GND to form a low pass filter. ADC Function - VOUT Noise The ADC can appear to return erroneous readings when connected to a power supply DC/DC converter output exhibiting a low frequency noise component. Adding additional filter capacitance to the VMX pins 15, 18 and 21 can reduce this effect by lowering the corner frequency of the low pass filter (C25, C26 and C27 in Figure 6). The maximum recommended value is 150nF. Figure 10 displays the SMH4046 shutting the power supplies (Force Shutdown) during the Sequence-On interval due to the time-out of the Sequence Termination Timer. Figure 10: SMH4046EV Forced Sequence-Off Tektronix TDS3054: Time/Horizontal division = 40mS Ch 1(2V/Div) = 12V output (Yellow trace) Ch 2 (1V/Div) = 1.8V DC-DC converter output (Blue trace) Ch 3 (1V/Div) = 2.5V DC-DC converter output (Purple trace) Ch 4 (1V/Div) = 5.0V output (Green trace) Summit Microelectronics, Inc 2082 1.7 08/23/04 16 SMH4046 Preliminary Information I2C 2-WIRE SERIAL INTERFACE Programming Information I2C Bus Interface The I2C bus interface is a standard two-wire serial protocol that allows communication between integrated circuits. The data line (SDA) is a bidirectional I/O; the clock line (SCL) runs at speeds of up to 400kHz. The SMH4046 supports a 100 kHz clock rate. The SDA line must be connected to a positive logic supply through a pull-up resistor located on the bus. Start and Stop Conditions Both the SDA and SCL pins remain high when the bus is not busy. Data transfers between devices may be initiated with a Start condition. A high-to-low transition of the SDA input while the SCL pin is high is defined as a Start condition. A low-to-high transition SDA while SCL is high is defined as a Stop condition. Figure 11 shows a timing diagram of the start and stop conditions. Acknowledge Data is always transferred in bytes. Acknowledge (ACK) is used to indicate a successful data transfer. The transmitting device releases the bus after transmitting eight bits. During the ninth clock cycle the Receiver pulls the SDA line low to acknowledge that it received the eight bits of data. This is shown by the ACK callout in Figure 12. When the last byte has been transferred to the Master during a read of the SMH4046, the Master leaves SDA high for a Not Acknowledge (NACK) cycle. This causes the SMH4046 part to stop sending data, and the Master issues a Stop on the clock pulse following the NACK. Figure 12 - Acknowledge Timing Read and Write Figure 11 - Start and Stop Conditions Master/Slave Protocol The master/slave protocol defines any device that sends data onto the bus as a transmitter, and any device that receives data as a receiver. The device controlling data transmission is called the Master, and the controlled device is called the Slave. In all cases the SMH4046 is referred to as a Slave device since it never initiates any data transfers. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during clock high time, because a change on the data line while SCL is high is interpreted as either a Start or a Stop condition. The first byte from a Master is always made up of a 7bit Slave address and the Read/Write (R/W) bit. The R/W bit tells the Slave whether the Master is reading data from the bus or writing data to the bus (1 = Read, 0 = Write). The first four of the seven address bits are called the Device Type Identifier (DTI). In the case of the SMH4046, the next two bits are Bus Address values, used to distinguish multiple devices on a common bus. The seventh bit of the slave address represents the ninth bit of the word address. The SMH4046 issues an Acknowledge after recognizing a Start condition and its DTI. Figure 13 shows an example of a typical master address byte transmission. Figure 13 - Typical Master Address Byte Transmission Summit Microelectronics, Inc 2082 1.7 08/23/04 17 SMH4046 Preliminary Information I2C 2-WIRE SERIAL INTERFACE (CONTINUED) During a read by the Master device, the SMH4046 transmits eight bits of data, then releases the SDA line, and monitors the line for an Acknowledge signal. If an Acknowledge is detected, and no Stop condition is generated by the Master, the SMH4046 continues to transmit data. If an Acknowledge is not detected (NACK), the SMH4046 terminates any subsequent data transmission. The read transfer protocol on SDA is shown in Figure 14. Random Access Read Random address read operations (Figure 16) allow the Master to access any memory location in a random fashion. This operation involves a two-step process. First, the Master issues a Write command which includes the Start condition and the Slave address field (with the R/W bit set to Write) followed by the address of the word it is to read. This procedure sets the internal address counter of the SMH4046 to the desired address. After the word address Acknowledge is received by the Master, it immediately reissues a Start condition followed by another Slave address field with the R/W bit set to Read. The SMH4046 responds with an Acknowledge and then transmits the 8 data bits stored at the addressed location. At this point, the Master sets the SDA line to NACK and generates a Stop condition. The SMH4046 discontinues data transmission and reverts to its standby power mode. Sequential Reads Sequential reads (Figure 16) can be initiated as either a current address read or a random access read. The first word is transmitted as with the other byte Read modes (current address byte Read or random address byte Read). However, the Master now responds with an Acknowledge, indicating that it requires additional data from the SMH4046. The SMH4046 continues to output data for each Acknowledge received. The Master sets the SDA line to NACK and generates a Stop condition. During a sequential Read operation the internal address counter is automatically incremented with each Acknowledge signal. Figure 15 - Write Protocol For Read operations all address bits are incremented, allowing the entire array to be read using a single Read command. After a count of the last memory address the address counter rolls over and the memory continues to output data. Figure 14 - Read Protocol During a Master write, the SMH4046 receives eight bits of data, then generates an Acknowledge signal. The device continues to generate the ACK condition on SDA until a Stop condition is generated by the Master. The write transfer protocol on SDA is shown in Figure 15. Summit Microelectronics, Inc 2082 1.7 08/23/04 18 SMH4046 Preliminary Information I C 2-WIRE SERIAL INTERFACE (CONTINUED) 2 Figure 16 - Typical EE Memory Write and Random Read Operations FPGA Configuration Interface The FPGA interface is used to perform configuration of industry standard FPGAs by loading application specific data into the FPGA configuration memory via the SMH4046 FPGA interface. To enable the FPGA interface option, Bit 7 of configuration register hex0C must be set to a 1. Bits [2:0] of register hex84, slave address 1001are write/read bits that are mapped to output pins FPGA_DCLK, FPGA_DO, and FPGA_NCFG, respectively. A write to these bits will result in the same corresponding state on the output pins. Bits [7:6] are mapped to input pins FPGA_NSTS and FPGA_CFGDONE, respectively. The state of these pins is reflected in the corresponding bits and can be read. The function of each pin is described in Table 1. For more information, see the FPGA data sheet for configuration options. Symbol FPGA_NSTS FPGA_CFGD ONE FPGA_NCFG FPGA_DO FPGA_DCLK Type I I O O O Description FPGA configuration status input pin FPGA_CFGDONE indicates completion of the configuration process. FPGA_NCFG is a configuration control output. A low transition resets the target device; a low-to-high transition begins configuration. FPGA_DO provides preamble and configuration data to downstream devices in a daisy-chain. FPGA Configuration clock output. Clock output used to clock configuration data using pin FPGA_DO. TABLE 1 - FPGA Configuration interface Summit Microelectronics, Inc 2082 1.7 08/23/04 19 SMH4046 Preliminary Information I C 2-WIRE SERIAL INTERFACE (CONTINUED) Register Access The SMH4046 contains a 2-wire bus interface for register access as explained in the previous section. This bus is highly configurable, while maintaining the industry standard protocol. The SMH4046 responds to one of two selectable Device Type Addresses: 1010BIN, generally assigned to NV-memories and the default address for the SMH4046, or 1011BIN. The Device Type Address is assigned by programming bit 3 of Register 0x0E. Slave Address Bus Address 2 The configuration registers may be locked out by setting bit 7 of register 0x0D high. This is a one-time, non-reversible operation. The SMH4046 has two virtual address pins, A[1:0] (set with R0E[1:0]), associated with the 2-wire bus. Register Type 1001BIN A2 A1 A0 Command and Status Registers, ADC Conversion Readout 1010BIN or 1011BIN A2 A1 0 A2 A1 1 2-k Bits of General-Purpose Memory Configuration Registers Table 2 - Address bytes used by the SMH4046. Summit Microelectronics, Inc 2082 1.7 08/23/04 20 SMH4046 Preliminary Information I C PROGRAMMING INFORMATION (CONTINUED) 2 Master S T A R T 1 0 1 S A 0 Bus Address A 2 A 1 C 7 A C K C 6 Configuration Register Address W C 5 C 4 C 3 C 2 C 1 C 0 A C K D 7 D 6 D 5 Data D 4 D 3 D 2 D 1 D 0 A C K S T O P 1 Slave Figure 17 - Configuration Register Byte Write Master S T A R T 1 0 1 S A 0 Bus Address A 2 A 1 C 7 A C K C 6 Configuration Register Address C 5 C 4 C 3 C 2 C 1 C 0 A C K S T A R T 1 0 1 S A 0 Bus Address A 2 1 W 1 1 R A C K Slave Master D 7 Slave D 6 D 5 Data (1) D 4 D 3 D 2 D 1 D 0 A C K D 7 D 6 D 5 D 2 D 1 D 0 A C K D 7 D 6 D 5 Data (n) D 4 D 3 D 2 D 1 D 0 N A C K S T O P Figure 18 - Configuration Register Read Summit Microelectronics, Inc 2082 1.7 08/23/04 21 SMH4046 Preliminary Information I2C PROGRAMMING INFORMATION (CONTINUED) S T A R T 1 Slave 0 1 S A 0 Master Bus Address A 2 A 1 C 7 A C K C 6 Configuration Register Address W C 5 C 4 C 3 C 2 C 1 C 0 A C K D 7 D 6 D 5 Data D 4 D 3 D 2 D 1 D 0 A C K S T O P 0 Figure 19 - General Purpose Memory Byte Write S T A R T 1 Slave 0 1 S A 0 S T A R T C 1 C 0 A C K 1 0 1 S A 0 Master Bus Address A 2 A 1 C 7 A C K C 6 Configuration Register Address W C 5 C 4 C 3 C 2 Bus Address A 2 0 / 1 0 0 R A C K Master D 7 Slave D 6 D 5 Data (1) D 4 D 3 D 2 D 1 D 0 A C K D 7 D 6 D 5 D 2 D 1 D 0 A C K D 7 D 6 D 5 Data (n) D 4 D 3 D 2 D 1 D 0 N A C K S T O P Figure 20 - General Purpose Memory Read Summit Microelectronics, Inc 2082 1.7 08/23/04 22 SMH4046 Preliminary Information I2C PROGRAMMING INFORMATION (CONTINUED) S T A R T 1 Slave 0 0 1 Master Bus Address A 2 A 1 Command Register Address W A C K 0 0 0 0 0 0 0 0 A C K D 7 D 6 D 5 Data D 4 D 3 D 2 D 1 D 0 A C K S T O P 0 Figure 21 - Command Register Write S T A R T 1 Slave 0 0 1 S T A R T 1 0 A C K 1 0 0 1 Master Bus Address A 2 A 1 Status Register Address W A C K 0 0 0 0 0 0 Bus Address A 2 A 1 A 0 0 R A C K Master D 7 Slave D 6 D 5 Data (1) D 4 D 3 D 2 D 1 D 0 A C K D 7 D 6 D 5 D 2 D 1 D 0 A C K D 7 D 6 D 5 Data (n) D 4 D 3 D 2 D 1 D 0 N A C K S T O P Figure 22 - Status Register Read Summit Microelectronics, Inc 2082 1.7 08/23/04 23 SMH4046 Preliminary Information I2C DEVELOPMENT HARDWARE & SOFTWARE The end user can obtain the Summit SMX3200 programming system for device prototype development. The SMX3200 system consists of a programming Dongle, cable and WindowsTM GUI software. It can be ordered on the website or from a local representative. The SMX3200 programming Dongle/cable directly between a PC's parallel port and application. The device is then configured via an intuitive graphical user interface drop-down menus. interfaces the target on-screen employing The Windows GUI software will generate the data and send it in I2C serial bus format so that it can be directly downloaded to the SMH4046 via the programming Dongle and cable. An example of the connection interface is shown in Figure 23. When design prototyping is complete, the software can generate a HEX data file that should be transmitted to Summit for approval. Summit will then assign a unique customer ID to the HEX code and program production devices before the final electrical test operations. This will ensure proper device operation in the end application. 5V Supply D1 1N4148 Top view of straight 0.1" x 0.1 closed-side connector. SMX3200 interface cable connector Pin 10, Reserved Pin 8, Reserved Pin 6, MR# Pin 4, SDA Pin 2, SCL Pin 9, 5V Pin 7, 10V Pin 5, Reserved Pin 3, GND Pin 1, GND VCC5V(VDD) SMH4046 SDA SCL 10 8 6 4 2 9 7 5 3 1 0.1 F GND Figure 23 - SMX3200 Programmer I2C serial bus connections to program the SMH4046. The latest revisions of all software and an application brief describing the SMX3200 is available from the website at: http://www.summitmicro.com/tech_support/tech.htm#GUI Summit Microelectronics, Inc 2082 1.7 08/23/04 24 SMH4046 Preliminary Information CONFIGURATION REGISTERS Configuration Registers: The configuration registers are accessible via the I2C interface at slave address 1010 or 1011 and 1001. These registers determine which features of the device are active, set voltage sensing threshold levels, and define the programmable output logic. The following tables describe the configuration register bits in detail. The following registers are accessed using slave address 101 SA0 A2 A1 1 (SA0 = C_0E[3]). Register R00 - VREF nominal settings. Bits D[7:6] are unused and should be set to 00. Bits D[5:4] control the Ch C VREF value. Bits D[3:2] control Ch B VREF and Bits D[1:0] control Ch A VREF. D7 0 Register R00 D6 D5 0 0 0 1 1 D4 0 1 0 1 D3 D2 D1 D0 Action Unused. Ch C VREF=0.75 V Ch C VREF=1.0 V Ch C VREF=1.25 V Ch C VREF=2.0 V Ch B VREF selection Nominal 1 1 Ch A VREF selection Nominal 1 1 Register R01 - Channel A Nominal Setting. Bits D[7:0] control the Channel A Margin Nominal setting. The DC Control Voltage setting bits (C[7:0]) are set using C[7:0] = 256 * VREF_CNTL / DC Control Voltage. VREF_CNTL is from register R00. Register R01 D7 D6 D5 C7 C6 C5 D4 C4 D3 C3 D2 C2 D1 C1 D0 C0 Action Channel A Margin Nominal Bits [7:0] Register R02 - Channel C Nominal Setting. Bits D[7:0] control the Channel C Margin Nominal setting Register R02 D7 D6 D5 C7 C6 C5 D4 C4 D3 C3 D2 C2 D1 C1 D0 C0 Action Channel C Margin Nominal Bits [7:0] Register R03 - Channel B Nominal Setting. Bits D[7:0] control the Channel B Margin Nominal setting D7 C7 Register R03 D6 D5 C6 C5 D4 C4 D3 C3 D2 C2 D1 C1 D0 C0 Action Channel B Margin Nominal Bits [7:0] Summit Microelectronics, Inc 2082 1.7 08/23/04 25 SMH4046 Preliminary Information CONFIGURATION REGISTERS (CONTINUED) Register R04 - Over-Current Configuration. Bit D[7] and D[5] are unused. Bit D[6] controls if OC causes an IRQ and D[4] controls if OC causes a FAULT. Bits D[3:0] control the overcurrent Delay. Register R04 D7 D6 D5 0 0 1 0 D4 0 1 D3 0 1 D2 0 1 D1 0 1 D0 0 1 Action Unused OC does not cause an IRQ OC causes an IRQ Unused OC does not cause a FAULT OC causes a FAULT Minimum Overcurrent Delay = 5.5s, 1LSB=3s Maximum Overcurrent Delay = 50.5s Register R05 - Overcurrent configuration and fault latch. Bits D[7:6] control the VDD differential level that causes an OC. Bits D[5:4] control the VCC3 differential level that causes an OC. Bit D[3] controls the 5V OC detection. Bit D[2] controls the 3V OC detection. Bit D[1] controls the FAULT output latch and D[0] is unused. Register R05 D7 D6 D5 0 0 1 1 0 1 0 1 0 0 1 1 D4 0 1 0 1 D3 0 1 D2 0 1 D1 0 1 D0 0 Action 50mV differential between VDD and CARD5V causes OC 100mV differential between VDD and CARD5V causes OC 150mV differential between VDD and CARD5V causes OC 250mV differential between VDD and CARD5V causes OC 50mV differential between VCC3 and CARD3V causes OC 100mV differential between VCC3 and CARD3V causes OC 150mV differential between VCC3 and CARD3V causes OC 250mV differential between VCC3 and CARD3V causes OC OC detection on 5V channel OFF OC detection on 5V channel ON OC detection on 3V channel OFF OC detection on 3V channel ON Fault output is unlatched Fault output is latched Unused Summit Microelectronics, Inc 2082 1.7 08/23/04 26 SMH4046 Preliminary Information CONFIGURATION REGISTERS (CONTINUED) Register R06 -Healthy Triggers. Register R06 D6 D5 0 1 0 1 - D7 0 1 - D4 0 1 - D3 0 1 - D2 0 1 - D1 0 1 - D0 0 1 Action Ext Temp fault does not cause a HEALTHY. Ext Temp fault causes a HEALTHY. Internal Temp fault does not cause a HEALTHY. Internal Temp fault causes a HEALTHY. CARD12V fault does not cause a HEALTHY. CARD12V fault causes a HEALTHY. CARD5V fault does not cause a HEALTHY. CARD5V fault causes a HEALTHY. CARD3V fault does not cause a HEALTHY. CARD3V fault causes a HEALTHY. VMC fault does not cause a HEALTHY. VMC fault causes a HEALTHY. VMB fault does not cause a HEALTHY. VMB fault causes a HEALTHY. VMA fault does not cause a HEALTHY. VMA fault causes a HEALTHY. Register R0C - Misc Config Register R0C D6 D5 0 1 0 0 - D7 0 1 - D4 0 0 - D3 0 1 - D2 0 1 - D1 0 1 - D0 0 1 Action FPGA feature disabled. FPGA selected from register. ADOC fast convergence disabled. ADOC fast convergence enabled. Unused Unused Unused Unused VGATE charge pump not always on. VGATE charge pump always on. Channel C Trim polarity normal. Channel C Trim polarity inverse. Channel B Trim polarity normal. Channel B Trim polarity inverse. Channel A Trim polarity normal. Channel A Trim polarity inverse. Summit Microelectronics, Inc 2082 1.7 08/23/04 27 SMH4046 Preliminary Information CONFIGURATION REGISTERS (CONTINUED) Register R0D - Misc Config. Register R0D D7 D6 D5 0 1 0 1 0 1 D4 - D3 - D2 - D1 - D0 - 0 1 0 1 0 1 0 1 0 1 Action Config registers unlocked. Config registers locked. Don't wait for temp within spec. Wait for temp within spec. VGATE slew rate is 250V/S. VGATE slew rate is 1000V/S. VGATE5 configured as an open drain output. VGATE5 configured as a high voltage output. VGATE3 configured as an open drain output. VGATE3 configured as a high voltage output. Channel C DC Control/Margining disabled. Channel C DC Control/Margining enabled. Channel B DC Control/Margining disabled. Channel B DC Control/Margining enabled. Channel A DC Control/Margining disabled. Channel A DC Control/Margining enabled. Register R0E - Command and Control Configuration Settings Register R0E D6 D5 0 1 0 1 0 0 1 1 - D7 0 0 1 1 - D4 0 1 0 1 - D3 0 1 - D2 0 1 - D1 0 1 1 1 D0 0 1 Action Sequence termination time = 40mS Sequence termination time = 75mS Sequence termination time = 150mS Sequence termination time = 300mS RESET timeout period = 1mS RESET timeout period = 40mS RESET timeout period = 150mS RESET timeout period = 300mS Slave address = 1010 Slave address = 1011 A2 = 0 A2 = pin level A1 = 0 A1 = 1 A0 = 0 A0 = 1 Summit Microelectronics, Inc 2082 1.7 08/23/04 28 SMH4046 Preliminary Information CONFIGURATION REGISTERS (CONTINUED) Register R0F - Command and Control Configuration Settings Register R0F D6 D5 0 1 0 1 - D7 0 1 - D4 0 1 - D3 0 1 - D2 0 1 - D1 0 1 - D0 0 1 Action Don't wait for VCC3 out of fault before sequencing. Wait for VCC3 out of fault before sequencing. No write command required for Active Control. Write command required for Active Control. Auto Monitor actions wait for ADOC ready. Auto Monitor actions don't wait for ADOC ready. Sequence off in reverse order. Sequence off in same order. Power off required to clear a Forced Shutdown. Power off not required to clear a Forced Shutdown. Abort not allowed during power off. Abort allowed during power off. Don't wait for 12VIN out of fault before sequencing. Wait for 12VIN out of fault before sequencing. Don't wait for VDD out of fault before sequencing. Wait for VDD out of fault before sequencing. Register R10 - PUPA Configuration. D7 0 1 Register R10 D5 D6 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 D4 0 1 0 1 0 1 0 1 D3 0 0 1 1 D2 0 1 0 1 D1 0 0 1 1 D0 0 1 0 1 Action Channel A not used in sequencing Channel A used in sequencing Channel A assigned to sequence position 0 Channel A assigned to sequence position 1 Channel A assigned to sequence position 2 Channel A assigned to sequence position 3 Channel A assigned to sequence position 4 Channel A assigned to sequence position 5 Unused Null position (not used in sequencing) Channel A power-on delay time = 1mS Channel A power-on delay time = 20mS Channel A power-on delay time = 40mS Channel A power-on delay time = 75mS Channel A power-off delay time = 1mS Channel A power-off delay time = 20mS Channel A power-off delay time = 40mS Channel A power-off delay time = 75mS Summit Microelectronics, Inc 2082 1.7 08/23/04 29 SMH4046 Preliminary Information CONFIGURATION REGISTERS (CONTINUED) Register R11 -PUPB Configuration. D7 0 1 Register R11 D5 D6 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 D4 0 1 0 1 0 1 0 1 D3 0 0 1 1 D2 0 1 0 1 D1 0 0 1 1 D0 0 1 0 1 Action Channel B not used in sequencing Channel B used in sequencing Channel B assigned to sequence position 0 Channel B assigned to sequence position 1 Channel B assigned to sequence position 2 Channel B assigned to sequence position 3 Channel B assigned to sequence position 4 Channel B assigned to sequence position 5 Unused Null position (not used in sequencing) Channel B power-on delay time = 1mS Channel B power-on delay time = 20mS Channel B power-on delay time = 40mS Channel B power-on delay time = 75mS Channel B power-off delay time = 1mS Channel B power-off delay time = 20mS Channel B power-off delay time = 40mS Channel B power-off delay time = 75mS Register R12 - PUPC Configuration Register R12 D5 D6 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 - D7 0 1 - D4 0 1 0 1 0 1 0 1 - D3 0 0 1 1 - D2 0 1 0 1 - D1 0 0 1 1 D0 0 1 0 1 Action Channel C not used in sequencing Channel C used in sequencing Channel C assigned to sequence position 0 Channel C assigned to sequence position 1 Channel C assigned to sequence position 2 Channel C assigned to sequence position 3 Channel C assigned to sequence position 4 Channel C assigned to sequence position 5 Unused Null position (not used in sequencing) Channel C power-on delay time = 1mS Channel C power-on delay time = 20mS Channel C power-on delay time = 40mS Channel C power-on delay time = 75mS Channel C power-off delay time = 1mS Channel C power-off delay time = 20mS Channel C power-off delay time = 40mS Channel C power-off delay time = 75mS Summit Microelectronics, Inc 2082 1.7 08/23/04 30 SMH4046 Preliminary Information CONFIGURATION REGISTERS (CONTINUED) Register R13 - VGATE3 Configuration Register R13 D6 D5 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 - D7 0 1 - D4 0 1 0 1 0 1 0 1 - D3 0 0 1 1 - D2 0 1 0 1 - D1 0 0 1 1 D0 0 1 0 1 Action Channel VGATE3 not used in sequencing Channel VGATE3 used in sequencing Channel VGATE3 assigned to sequence position 0 Channel VGATE3 assigned to sequence position 1 Channel VGATE3 assigned to sequence position 2 Channel VGATE3 assigned to sequence position 3 Channel VGATE3 assigned to sequence position 4 Channel VGATE3 assigned to sequence position 5 Unused Null position (not used in sequencing) Channel VGATE3 power-on delay time = 1mS Channel VGATE3 power-on delay time = 20mS Channel VGATE3 power-on delay time = 40mS Channel VGATE3 power-on delay time = 75mS Channel VGATE3 power-off delay time = 1mS Channel VGATE3 power-off delay time = 20mS Channel VGATE3 power-off delay time = 40mS Channel VGATE3 power-off delay time = 75mS Register R14 - VGATE5 Configuration Register R14 D5 D6 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 - D7 0 1 - D4 0 1 0 1 0 1 0 1 - D3 0 0 1 1 - D2 0 1 0 1 - D1 0 0 1 1 D0 0 1 0 1 Action Channel VGATE5 not used in sequencing Channel VGATE5 used in sequencing Channel VGATE5 assigned to sequence position 0 Channel VGATE5 assigned to sequence position 1 Channel VGATE5 assigned to sequence position 2 Channel VGATE5 assigned to sequence position 3 Channel VGATE5 assigned to sequence position 4 Channel VGATE5 assigned to sequence position 5 Unused Null position (not used in sequencing) Channel VGATE5 power-on delay time = 1mS Channel VGATE5 power-on delay time = 20mS Channel VGATE5 power-on delay time = 40mS Channel VGATE5 power-on delay time = 75mS Channel VGATE5 power-off delay time = 1mS Channel VGATE5 power-off delay time = 20mS Channel VGATE5 power-off delay time = 40mS Channel VGATE5 power-off delay time = 75mS Summit Microelectronics, Inc 2082 1.7 08/23/04 31 SMH4046 Preliminary Information CONFIGURATION REGISTERS (CONTINUED) Register R15 - DRVREN# Configuration. Register R15 D5 D6 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 - D7 0 1 - D4 0 1 0 1 0 1 0 1 - D3 0 0 1 1 - D2 0 1 0 1 - D1 0 0 1 1 D0 0 1 0 1 Action Channel DRVREN# not used in sequencing Channel DRVREN# used in sequencing Channel DRVREN# assigned to sequence position 0 Channel DRVREN# assigned to sequence position 1 Channel DRVREN# assigned to sequence position 2 Channel DRVREN# assigned to sequence position 3 Channel DRVREN# assigned to sequence position 4 Channel DRVREN# assigned to sequence position 5 Unused Null position (not used in sequencing) Channel DRVREN# power-on delay time = 1mS Channel DRVREN# power-on delay time = 20mS Channel DRVREN# power-on delay time = 40mS Channel DRVREN# power-on delay time = 75mS Channel DRVREN# power-off delay time = 1mS Channel DRVREN# power-off delay time = 20mS Channel DRVREN# power-off delay time = 40mS Channel DRVREN# power-off delay time = 75mS Register R18, 1A, 1C, 1E - Write Only MARGIN_COMMAND . Register R18 D7 D6 D5 D4 D3 D2 D1 D0 Action Unused 0 Unused 0 Channel A Command = Margin Nominal 0 0 Channel A Command = Margin Nominal 0 1 Channel A Command = Margin Low 1 0 Channel A Command = Margin High 1 1 Channel C Command = Margin Nominal 0 0 Channel C Command = Margin Nominal 0 1 Channel C Command = Margin Low 1 0 Channel C Command = Margin High 1 1 Channel B Command = Margin Nominal 0 0 Channel B Command = Margin Nominal 0 1 Channel B Command = Margin Low 1 0 Channel B Command = Margin High 1 1 Summit Microelectronics, Inc 2082 1.7 08/23/04 32 SMH4046 Preliminary Information CONFIGURATION REGISTERS (CONTINUED) Register R30 - VREF Margin Channels A-C. Register R30 D6 D5 0 0 0 1 1 - D7 0 - D4 0 1 0 1 - D3 0 0 1 1 - D2 0 1 0 1 - D1 0 0 1 1 D0 0 1 0 1 Action Unused Unused Channel C VREF Margin High Selection = 0.75V Channel C VREF Margin High Selection = 1.00V Channel C VREF Margin High Selection = 1.25V Channel C VREF Margin High Selection = 2.00V Channel B VREF Margin High Selection = 0.75V Channel B VREF Margin High Selection = 1.00V Channel B VREF Margin High Selection = 1.25V Channel B VREF Margin High Selection = 2.00V Channel A VREF Margin High Selection = 0.75V Channel A VREF Margin High Selection = 1.00V Channel A VREF Margin High Selection = 1.25V Channel A VREF Margin High Selection = 2.00V Register R31 - Channel A Margin High bits Register R31 D7 D6 D5 D4 D3 D2 C7 C6 C5 C4 C3 C2 Register R32 - Channel C Margin High bits Register R32 D7 D6 D5 D4 D3 D2 C7 C6 C5 C4 C3 C2 Register R33 - Channel B Margin High bits Register R33 D7 D6 D5 D4 D3 D2 C7 C6 C5 C4 C3 C2 D1 C1 D0 C0 Action Channel A Margin High Bits [7:0] D1 C1 D0 C0 Action Channel C Margin High Bits [7:0] D1 C1 D0 C0 Action Channel B Margin High Bits [7:0] Summit Microelectronics, Inc 2082 1.7 08/23/04 33 SMH4046 Preliminary Information CONFIGURATION REGISTERS (CONTINUED) Register R40 - VREF Margin Channels A-C. Register R40 D6 D5 0 0 0 1 1 - D7 0 - D4 0 1 0 1 - D3 0 0 1 1 - D2 0 1 0 1 - D1 0 0 1 1 D0 0 1 0 1 Action Unused Unused Channel C VREF Margin Low Selection = 0.75V Channel C VREF Margin Low Selection = 1.00V Channel C VREF Margin Low Selection = 1.25V Channel C VREF Margin Low Selection = 2.00V Channel B VREF Margin Low Selection = 0.75V Channel B VREF Margin Low Selection = 1.00V Channel B VREF Margin Low Selection = 1.25V Channel B VREF Margin Low Selection = 2.00V Channel A VREF Margin Low Selection = 0.75V Channel A VREF Margin Low Selection = 1.00V Channel A VREF Margin Low Selection = 1.25V Channel A VREF Margin Low Selection = 2.00V Register R41 - Channel A Margin Low bits Register R41 D7 D6 D5 D4 D3 D2 C7 C6 C5 C4 C3 C2 Register 42 - Channel C Margin Low bits Register R42 D7 D6 D5 D4 D3 D2 C7 C6 C5 C4 C3 C2 Register R43 - Channel B Margin Low bits Register R43 D7 D6 D5 D4 D3 D2 C7 C6 C5 C4 C3 C2 D1 C1 D0 C0 Action Channel A Margin Low Bits [7:0] D1 C1 D0 C0 Action Channel C Margin Low Bits [7:0] D1 C1 D0 C0 Action Channel B Margin Low Bits [7:0] Summit Microelectronics, Inc 2082 1.7 08/23/04 34 SMH4046 Preliminary Information CONFIGURATION REGISTERS (CONTINUED) Register R80, 88, 90, 98, A0, A8, B0, B8 - Channel A, B, C, CARD12V, CARD3V, CARD5V, VDD and 12VIN Limit Triggers, Limit Bits [9:8]. Register R80, 88, 90, 98, A0, A8, B0, B8 D6 D5 D4 D3 D2 D1 0 1 0 1 0 1 0 0 0 1 1 0 1 1 C9 D7 0 1 - D0 C8 Action Limit does not trigger a RST Limit triggers a RST Limit does not trigger an IRQ Limit triggers an IRQ Limit does not trigger a Power Down Limit triggers a Power Down Limit does not trigger a Forced Shutdown Limit triggers a Forced Shutdown Limit Consecutive Conversions for Fault = 1 Limit Consecutive Conversions for Fault = 2 Limit Consecutive Conversions for Fault = 4 Limit Consecutive Conversions for Fault = 6 Channel Low Limit 1 Bits [9:8] Register R81, 89, 91, 99, A1, A9, B1, B9 - Channel A, B, C, CARD12V, CARD3V, CARD5V, VDD and 12VIN Limit Settings [7:0]. Register R81, 89, 91, 99, A1, A9, B1, B9 D7 D6 D5 D4 D3 D2 D1 D0 Action Channel Low Limit 1 Bits [7:0] C7 C6 C5 C4 C3 C2 C1 C0 Register R82, 8A, 92, 9A, A2, AA, B2, BA - Channel A, B, C, CARD12V, CARD3V, CARD5V, VDD and 12VIN Limit Settings [9:8]. Register R82, 8A, 92, 9A, A2, AA, B2, BA D7 D6 D5 D4 D3 D2 D1 D0 Action Channel Low Limit 2 Bits [9:8] C9 C8 Register R83, 8B, 93, 9B, A3, AB, B3, BB- Channel A, B, C, CARD12V, CARD3V, CARD5V, VDD and 12VIN Limit Settings [7:0]. Register R83, 8B, 93, 9B, A3, AB, B3, BB D6 D5 D4 D3 D2 D1 C6 C5 C4 C3 C2 C1 D7 C7 D0 C0 Action Channel Low Limit 2 Bits [7:0] Register R84, 8C, 94, 9C, A4, AC, B4, BC- Channel A, B, C, CARD12V, CARD3V, CARD5V, VDD and 12VIN Limit Settings [9:8]. Register R84, 8C, 94, 9C, A4, AC, B4, BC D7 D6 D5 D4 D3 D2 D1 D0 Action Channel High Limit 1 Bits [9:8] C9 C8 Summit Microelectronics, Inc 2082 1.7 08/23/04 35 SMH4046 Preliminary Information CONFIGURATION REGISTERS (CONTINUED) Register R85, 8D, 95, 9D, A5, AD, B5, BD - Channel A, B, C, CARD12V, CARD3V, CARD5V, VDD and 12VIN Limit Settings [7:0]. Register R85, 8D, 95, 9D, A5, AD, B5, BD D7 D6 D5 D4 D3 D2 D1 D0 Action Channel High Limit 1 Bits [7:0] C7 C6 C5 C4 C3 C2 C1 C0 Register R86, 8E, 96, 9E, A6, AE, B6, BE - Channel A, B, C, CARD12V, CARD3V, CARD5V, VDD and 12VIN Limit Settings [9:8]. Register R86, 8E, 96, 9E, A6, AE, B6, BE D7 D6 D5 D4 D3 D2 D1 D0 Action Channel High Limit 2 Bits [9:8] C9 C8 Register R87, 8F, 97, 9F, A7, AF, B7, BF - Channel A, B, C, CARD12V, CARD3V, CARD5V, VDD and 12VIN Limit Settings [7:0]. Register R87, 8F, 97, 9F, A7, AF, B7, BF D7 D6 D5 D4 D3 D2 D1 D0 Action Channel High Limit 2 Bits [7:0] C7 C6 C5 C4 C3 C2 C1 C0 Register RC0 -VCC3 Low Limit 1 Triggers, Limit Bits [9:8]. Register RC0, C2, C4, C6 D6 D5 D4 0 1 0 1 0 1 - D7 0 1 - D3 0 0 1 1 - D2 0 1 0 1 - D1 C9 D0 C8 Action VCC3 Low Limit 1 does not trigger a RST VCC3 Low Limit 1 triggers a RST VCC3 Low Limit 1 does not trigger an IRQ VCC3 Low Limit 1 triggers an IRQ VCC3 Low Limit 1 does not trigger a Power Down. VCC3 Low Limit 1 triggers a Power Down VCC3 Low Limit 1 does not trigger a Fault VCC3 Low Limit 1 triggers a Fault VCC3 Low Limit 1 Consecutive Conversions for Fault = 1 VCC3 Low Limit 1 Consecutive Conversions for Fault = 2 VCC3 Low Limit 1 Consecutive Conversions for Fault = 4 VCC3 Low Limit 1 Consecutive Conversions for Fault = 6 VCC3 Low Low Limit 1 Bits [9:8] Register RC1- VCC3 Low Limit 1 Settings [7:0]. Register RC1 D7 D6 D5 D4 D3 D2 D1 C7 C6 C5 C4 C3 C2 C1 D0 C0 Action VCC3 Low limit 1 Bits[7:0] Summit Microelectronics, Inc 2082 1.7 08/23/04 36 SMH4046 Preliminary Information CONFIGURATION REGISTERS (CONTINUED) Register RC2 -VCC3 Low Limit 2 Triggers, Limit Bits [9:8]. Register C2 D6 D5 0 1 0 1 - D7 0 1 - D4 0 1 - D3 0 0 1 1 - D2 0 1 0 1 - D1 C9 D0 C8 Action VCC3 Low Limit 2 does not trigger a RST VCC3 Low Limit 2 triggers a RST VCC3 Low Limit 2 does not trigger an IRQ VCC3 Low Limit 2 triggers an IRQ VCC3 Low Limit 2 does not trigger a Power Down. VCC3 Low Limit 2 triggers a Power Down VCC3 Low Limit 2 does not trigger a Fault VCC3 Low Limit 2 triggers a Fault VCC3 Low Limit 2 Consecutive Conversions for Fault = 1 VCC3 Low Limit 2 Consecutive Conversions for Fault = 2 VCC3 Low Limit 2 Consecutive Conversions for Fault = 4 VCC3 Low Limit 2 Consecutive Conversions for Fault = 6 VCC3 Low Limit 2 Bits [9:8] Register RC3 - VCC3 Low Limit 2 Settings [7:0]. Register RC3 D6 D5 C6 C5 D7 C7 D4 C4 D3 C3 D2 C2 D1 C1 D0 C0 Action VCC3 Low limit 2 Bits[7:0] Summit Microelectronics, Inc 2082 1.7 08/23/04 37 SMH4046 Preliminary Information CONFIGURATION REGISTERS (CONTINUED) Register RC4 -VCC3 High Limit 1 Triggers, Limit Bits [9:8]. Register C4 D6 D5 0 1 0 1 - D7 0 1 - D4 0 1 - D3 0 0 1 1 - D2 0 1 0 1 - D1 C9 D0 C8 Action VCC3 High Limit 1 does not trigger a RST VCC3 High Limit 1 triggers a RST VCC3 High Limit 1 does not trigger an IRQ VCC3 High Limit 1 triggers an IRQ VCC3 High Limit 1 does not trigger a Power Down. VCC3 High Limit 1 triggers a Power Down VCC3 High Limit 1 does not trigger a Fault VCC3 High Limit 1 triggers a Fault VCC3 High Limit 1 Consecutive Conversions for Fault = 1 VCC3 High Limit 1 Consecutive Conversions for Fault = 2 VCC3 High Limit 1 Consecutive Conversions for Fault = 4 VCC3 High Limit 1 Consecutive Conversions for Fault = 6 VCC3 High Limit 1 Bits [9:8] Register RC5 - VCC3 High Limit 1 Settings [7:0]. Register RC5 D6 D5 C6 C5 D7 C7 D4 C4 D3 C3 D2 C2 D1 C1 D0 C0 Action VCC3 High limit 1 Bits[7:0] Summit Microelectronics, Inc 2082 1.7 08/23/04 38 SMH4046 Preliminary Information CONFIGURATION REGISTERS (CONTINUED) Register RC6 -VCC3 High Limit 2 Triggers, Limit Bits [9:8]. Register C6 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 C9 C8 Action VCC3 High Limit 2 does not trigger a RST VCC3 High Limit 2 triggers a RST VCC3 High Limit 2 does not trigger an IRQ VCC3 High Limit 2 triggers an IRQ VCC3 High Limit 2 does not trigger a Power Down. VCC3 High Limit 2 triggers a Power Down VCC3 High Limit 2 does not trigger a Fault VCC3 High Limit 2 triggers a Fault VCC3 High Limit 2 Consecutive Conversions for Fault = 1 VCC3 High Limit 2 Consecutive Conversions for Fault = 2 VCC3 High Limit 2 Consecutive Conversions for Fault = 4 VCC3 High Limit 2 Consecutive Conversions for Fault = 6 VCC3 High Limit 2 Bits [9:8] Register RC7 - VCC3 High Limit 2 Settings [7:0]. Register RC7 D7 D6 D5 D4 D3 D2 D1 C7 C6 C5 C4 C3 C2 C1 D0 C0 Action VCC3 High limit 2 Bits[7:0] Register RC8- VTEMP Low Limit 1 Triggers, Limit Bits [9:8]. Register RC8 D7 D6 D5 D4 D3 D2 D1 D0 Action VTEMP Low Limit 1 does not trigger a RST 0 VTEMP Low Limit 1 triggers a RST 1 VTEMP Low Limit 1 does not trigger an IRQ 0 VTEMP Low Limit 1 triggers an IRQ 1 VTEMP Low Limit 1 does not trigger a Pwr. Dn. 0 VTEMP Low Limit 1 triggers a Power Down 1 VTEMP Low Limit 1 does not trigger a Fault 0 VTEMP Low Limit 1 triggers a Fault 1 VTEMP Low Limit 1 Consecutive Conversions for 0 0 Fault = 1 VTEMP Low Limit 1 Consecutive Conversions for 0 1 Fault = 2 VTEMP Low Limit 1 Consecutive Conversions for 1 0 Fault = 4 VTEMP Low Limit 1 Consecutive Conversions for 1 1 Fault = 6 VTEMP Low Limit 1 Bits [9:8] C9 C8 Summit Microelectronics, Inc 2082 1.7 08/23/04 39 SMH4046 Preliminary Information CONFIGURATION REGISTERS (CONTINUED) Register RC9- VTEMP Low Limit 1 Settings [7:0]. Register RC9 D7 D6 D5 C7 C6 C5 D4 C4 D3 C3 D2 C2 D1 C1 D0 C0 Action VTEMP Low Limit 1 Bits[7:0] Register RCA- VTEMP Low Limit 2 Triggers, Limit Bits [9:8]. Register RCA D6 D5 0 1 0 1 - D7 0 1 - D4 0 1 - D3 0 0 1 1 - D2 0 1 0 1 - D1 C9 D0 C8 Action VTEMP Low Limit 2 does not trigger a RST VTEMP Low Limit 2 triggers a RST VTEMP Low Limit 2 does not trigger an IRQ VTEMP Low Limit 2 triggers an IRQ VTEMP Low Limit 2 does not trigger a Pwr. Dn. VTEMP Low Limit 2 triggers a Power Down VTEMP Low Limit 2 does not trigger a Fault VTEMP Low Limit 2 triggers a Fault VTEMP Low Limit 2 Consecutive Conversions for Fault = 1 VTEMP Low Limit 2 Consecutive Conversions for Fault = 2 VTEMP Low Limit 2 Consecutive Conversions for Fault = 4 VTEMP Low Limit 2 Consecutive Conversions for Fault = 6 VTEMP Low Limit 2 Bits [9:8] Register RCB - VTEMP Low Limit 2 Settings [7:0]. Register RCB D7 D6 D5 C7 C6 C5 D4 C4 D3 C3 D2 C2 D1 C1 D0 C0 Action VTEMP Low Limit 2 Bits[7:0] Summit Microelectronics, Inc 2082 1.7 08/23/04 40 SMH4046 Preliminary Information CONFIGURATION REGISTERS (CONTINUED) Register RCC- VTEMP High Limit 1 Triggers, Limit Bits [9:8]. Register RCC D7 D6 D5 D4 D3 D2 D1 D0 Action VTEMP High Limit 1 does not trigger a RST 0 VTEMP High Limit 1 triggers a RST 1 VTEMP High Limit 1 does not trigger an IRQ 0 VTEMP High Limit 1 triggers an IRQ 1 VTEMP High Limit 1 does not trigger a Power Down 0 VTEMP High Limit 1 triggers a Power Down 1 VTEMP High Limit 1 does not trigger a Fault 0 VTEMP High Limit 1 triggers a Fault 1 VTEMP High Limit 1 Consecutive Conversions for 0 0 Fault = 1 VTEMP High Limit 1 Consecutive Conversions for 0 1 Fault = 2 VTEMP High Limit 1 Consecutive Conversions for 1 0 Fault = 4 VTEMP High Limit 1 Consecutive Conversions for 1 1 Fault = 6 VTEMP High Limit 1 Bits [9:8] C9 C8 Register RCD - VTEMP High Limit 1 Settings [7:0]. Register RCD D7 D6 D5 D4 D3 D2 D1 C7 C6 C5 C4 C3 C2 C1 D0 C0 Action VTEMP High Limit 1 Bits[7:0] Register RCE- VTEMP High Limit 2 Triggers, Limit Bits [9:8]. Register RCE D7 D6 D5 D4 D3 D2 D1 D0 Action VTEMP High Limit 2 does not trigger a RST 0 VTEMP High Limit 2 triggers a RST 1 VTEMP High Limit 2 does not trigger an IRQ 0 VTEMP High Limit 2 triggers an IRQ 1 VTEMP High Limit 2 does not trigger a Pwr. Dn. 0 VTEMP High Limit 2 triggers a Power Down 1 VTEMP High Limit 2 does not trigger a Fault 0 VTEMP High Limit 2 triggers a Fault 1 VTEMP High Limit 2 Consecutive Conversions for 0 0 Fault = 1 VTEMP High Limit 2 Consecutive Conversions for 0 1 Fault = 2 VTEMP High Limit 2 Consecutive Conversions for 1 0 Fault = 4 VTEMP High Limit 2 Consecutive Conversions for 1 1 Fault = 6 VTEMP High Limit 2 Bits [9:8] C9 C8 Summit Microelectronics, Inc 2082 1.7 08/23/04 41 SMH4046 Preliminary Information CONFIGURATION REGISTERS (CONTINUED) Register RCF - VTEMP High Limit 2 Settings [7:0]. Register RCF D6 D5 C6 C5 D7 C7 D4 C4 D3 C3 D2 C2 D1 C1 D0 C0 Action VTEMP High Limit 2 Bits[7:0] Register RD0 - EXT_TEMP Low Limit 1 Triggers, Limit Bits [9:8]. Register RD0 D6 D5 0 1 0 1 - D7 0 1 - D4 0 1 - D3 0 0 1 1 - D2 0 1 0 1 - D1 C9 D0 C8 Action EXT_TEMP Low Limit 1 does not trigger a RST EXT_TEMP Low Limit 1 triggers a RST EXT_TEMP Low Limit 1 does not trigger an IRQ EXT_TEMP Low Limit 1 triggers an IRQ EXT_TEMP Low Limit 1 does not trigger a Power Down EXT_TEMP Low Limit 1 triggers a Power Down EXT_TEMP Low Limit 1 does not trigger a Fault EXT_TEMP Low Limit 1 triggers a Fault EXT_TEMP Low Limit 1 Consecutive Conversions for Fault = 1 EXT_TEMP Low Limit 1 Consecutive Conversions for Fault = 2 EXT_TEMP Low Limit 1 Consecutive Conversions for Fault = 4 EXT_TEMP Low Limit 1 Consecutive Conversions for Fault = 6 EXT_TEMP Low Limit 1 Bits [9:8] Register RD1- EXT_TEMP Low Limit 1 Settings [9:8]. Register RD1 D7 D6 D5 C7 C6 C5 D4 C4 D3 C3 D2 C2 D1 C1 D0 C0 Action EXT_TEMP Low Limit 1 Bits[7:0] Summit Microelectronics, Inc 2082 1.7 08/23/04 42 SMH4046 Preliminary Information CONFIGURATION REGISTERS (CONTINUED) Register RD2 - EXT_TEMP Low Limit 2 Triggers, Limit Bits [9:8]. Register RD2 D7 D6 D5 D4 D3 D2 D1 D0 Action EXT_TEMP Low Limit 2 does not trigger a RST 0 EXT_TEMP Low Limit 2 triggers a RST 1 EXT_TEMP Low Limit 2 does not trigger an IRQ 0 EXT_TEMP Low Limit 2 triggers an IRQ 1 EXT_TEMP Low Limit 2 does not trigger a Pwr Dwn 0 EXT_TEMP Low Limit 2 triggers a Power Down 1 EXT_TEMP Low Limit 2 does not trigger a Fault 0 EXT_TEMP Low Limit 2 triggers a Fault 1 EXT_TEMP Low Limit 2 Consecutive Conversions 0 0 for Fault = 1 EXT_TEMP Low Limit 2 Consecutive Conversions 0 1 for Fault = 2 EXT_TEMP Low Limit 2 Consecutive Conversions 1 0 for Fault = 4 EXT_TEMP Low Limit 2 Consecutive Conversions 1 1 for Fault = 6 EXT_TEMP Low Limit 2 Bits [9:8] C9 C8 Register RD3- EXT_TEMP Low Limit 2 Settings [7:0]. Register RD3 D7 D6 D5 D4 D3 D2 D1 D0 C7 C6 C5 C4 C3 C2 C1 C0 Action EXT_TEMP Low Limit 2 Bits [7:0] Register RD4 - EXT_TEMP High Limit 1 Triggers, Limit Bits [9:8]. Register RD4 D7 D6 D5 D4 D3 D2 D1 D0 Action EXT_TEMP High Limit 1 does not trigger a RST 0 EXT_TEMP High Limit 1 triggers a RST 1 EXT_TEMP High Limit 1 does not trigger an IRQ 0 EXT_TEMP High Limit 1 triggers an IRQ 1 EXT_TEMP High Limit 1 does not trigger a Pwr. Dn. 0 EXT_TEMP High Limit 1 triggers a Power Down 1 EXT_TEMP High Limit 1 does not trigger a Fault 0 EXT_TEMP High Limit 1 triggers a Fault 1 EXT_TEMP High Limit 1 Consecutive Conversions 0 0 for Fault = 1 EXT_TEMP High Limit 1 Consecutive Conversions 0 1 for Fault = 2 EXT_TEMP High Limit 1 Consecutive Conversions 1 0 for Fault = 4 EXT_TEMP High Limit 1 Consecutive Conversions 1 1 for Fault = 6 EXT_TEMP High Limit 1 Bits [9:8] C9 C8 Summit Microelectronics, Inc 2082 1.7 08/23/04 43 SMH4046 Preliminary Information CONFIGURATION REGISTERS (CONTINUED) Register RD5 - EXT_TEMP High Limit 1 Settings [9:8]. Register RD5 D7 D6 D5 D4 D3 D2 D1 D0 C7 C6 C5 C4 C3 C2 C1 C0 Action EXT_TEMP High Limit 1 Bits [7:0] Register RD6 - EXT_TEMP High Limit 2 Triggers, Limit Bits [9:8]. Register RD6 D7 D6 D5 D4 D3 D2 D1 D0 Action EXT_TEMP High Limit 2 does not trigger a RST 0 EXT_TEMP High Limit 2 triggers a RST 1 EXT_TEMP High Limit 2 does not trigger an IRQ 0 EXT_TEMP High Limit 2 triggers an IRQ 1 EXT_TEMP High Limit 2 does not trigger a Power 0 Down EXT_TEMP High Limit 2 triggers a Power Down 1 EXT_TEMP High Limit 2 does not trigger a Fault 0 EXT_TEMP High Limit 2 triggers a Fault 1 EXT_TEMP High Limit 2 Consecutive Conversions 0 0 for Fault = 1 EXT_TEMP High Limit 2 Consecutive Conversions 0 1 for Fault = 2 EXT_TEMP High Limit 2 Consecutive Conversions 1 0 for Fault = 4 EXT_TEMP High Limit 2 Consecutive Conversions 1 1 for Fault = 6 EXT_TEMP High Limit 2 Bits [9:8] C9 C8 Register RD7 - EXT_TEMP High Limit 1 Settings [7:0]. Register RD7 D7 D6 D5 D4 D3 D2 D1 D0 C7 C6 C5 C4 C3 C2 C1 C0 Action EXT_TEMP High Limit 2 Bits [7:0] Register RE0, E2, E4, E6, E8, EA - Channel A, B, C, CARD12, CARD3, CARD5 Off Limits [9:8]. Register RE0, E2, E4, E6, E8, EA D7 D6 D5 D4 D3 D2 D1 D0 Action Channel/CardX Off Limits [9:8] C9 C8 Register RE1, E3, E5, E7, E9, EB - Channel A, B, C, CARD12, CARD3, CARD5 Off Limits [7:0]. Register RE1 E3, E5, E7, E9, EB D7 D6 D5 D4 D3 D2 D1 D0 Action Channel/CardX Off Limits [7:0] C7 C6 C5 C4 C3 C2 C1 C0 Summit Microelectronics, Inc 2082 1.7 08/23/04 44 SMH4046 Preliminary Information CONFIGURATION REGISTERS (CONTINUED) Registers accessed using slave address 1001 A2 A1 A0. Register R00, 08, 10, 18, 20, 28, 30, 38, 40, 48, 50 - Channel A, B, C, CARD12V, CARD3V, CARD5V, VDD, 12VIN, VCC3, VTEMP, EXT_TEMP ADC Register Readout [9:8]. Register R00, 08, 10, 18, 20, 28, 30, 38, 40, 48, 50 D7 D6 D5 D4 D3 D2 D1 D0 Ch Ch Ch Ch Ch 0 0 0 C9 C8 Action Channel being read Unused Upper 2 bits of ADC readout Register R01, 09, 11, 19, 21, 29, 30, 39, 41, 49, 51- Channel A, B, C, CARD12V, CARD3V, CARD5V, VDD, 12VIN, VCC3, VTEMP, EXT_TEMP ADC Register Readout [7:0]. Register R01, 09, 11, 19, 21, 29, 30, 39, 41, 49, 51 D7 D6 D5 D4 D3 D2 D1 D0 C7 C6 C5 C4 C3 C2 C1 C0 Action Channel being read Register R80 Communication Interface Command and Control . Register R80 D7 D6 D5 D4 D3 D2 D1 D0 Action Does Nothing 0 0 0 0 Power-On command 1 0 0 0 Power-Off command 0 1 0 0 Forced Shutdown command 0 0 1 0 Command does not Clear IRQ 0 0 Command Clears IRQ 1 0 Sequenced Channels not out of Fault (Read Only) 0 0 Sequenced Channels out of Fault (Read Only) 1 0 Sequenced Channels not Below Off Limit (Read 0 0 Only) Sequenced Channels Below Off Limit (Read Only) 1 0 IRQ not Present (Read-Only) 0 0 IRQ Present (Read-Only) 1 0 Unused 0 Summit Microelectronics, Inc 2082 1.7 08/23/04 45 SMH4046 Preliminary Information CONFIGURATION REGISTERS (CONTINUED) Register R81 Status Registers (Fault [10:8]). Register R81 D7 D6 D5 D4 D3 D2 D1 0 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 0 0 0 0 0 1 1 Register R82 Status Registers (Fault [7:0]). Register R82 D7 D6 D5 D4 D3 D2 0 1 0 1 0 1 0 1 0 1 0 1 D0 0 1 Action Sequence not Aborted Sequence Aborted Sequence Position Aborted = 0 Sequence Position Aborted = 1 Sequence Position Aborted = 2 Sequence Position Aborted = 3 Sequence Position Aborted = 4 Sequence Position Aborted = 5 Unused [EXT_TEMP, Vtemp, VCC3] = No Fault [EXT_TEMP, Vtemp, VCC3] = Fault D1 0 1 D0 0 1 Action [12VIN, VDD, CARD5V, CARD3V, CARD12V, ChC, ChB, ChA] = No Fault [12VIN, VDD, CARD5V, CARD3V, CARD12V, ChC, ChB, ChA] = Fault Register R84 FPGA I/O. Register R84 D7 D6 D5 0 1 0 1 0 - D4 0 - D3 0 - D2 0 1 D1 0 1 - D0 0 1 Action FPGA_NSTS input FPGA_NSTS input FPGA_CFGDONE input FPGA_CFGDONE input Unused FPGA_DCLK Data output FPGA_DCLK Data output FPGA_D0 Data output FPGA_D0 Data output FPGA_NCFG Data output FPGA_NCFG Data output Summit Microelectronics, Inc 2082 1.7 08/23/04 46 SMH4046 Preliminary Information CONFIGURATION REGISTERS (CONTINUED) Register R85 Read-Only Margin Command. Register R85 D7 D6 D5 D4 D3 D2 0 1 0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 Register R87 Write Protect. Register R87 D7 D6 D5 D4 0 1 0 1 - D1 0 0 1 1 D0 0 1 0 1 Action DC Control not Ready DC Control Ready Unused Channel A Margin Nominal Channel A Margin Nominal Channel A Margin Low Channel A Margin High Channel C Margin Nominal Channel C Margin Nominal Channel C Margin Low Channel C Margin High Channel B Margin Nominal Channel B Margin Nominal Channel B Margin Low Channel B Margin High D3 0 D2 1 D1 0 D0 1 Action EEPROM Write Protected EEPROM Not Write Protected Config Write Protected Config Not Write Protected Register R88 Status Tracking Code. Register R88 D7 D6 D5 D4 D3 0 0 0 0 0 D2 0 D1 0 D0 1 Action U01 Summit Microelectronics, Inc 2082 1.7 08/23/04 47 SMH4046 Preliminary Information CONFIGURATION REGISTERS (CONTINUED) Register R8B Pin Polarity. Register R8B D7 D6 D5 D4 0 0 0 1 0 1 - D3 0 1 - D2 0 1 - D1 0 1 - D0 0 1 Action Unused [7:6] Healthy Active Low Healthy Active High Fault Active Low Fault Active High Reset Active Low Reset Active High HST_RST Active Low HST_RST Active High HST_PWR Active Low HST_PWR Active High FS Active Low FS Active High Register R8D Status Tracking Code. Register R8D D7 D6 D5 D4 D3 0 0 0 1 0 1 0 1 - D2 0 1 - D1 0 1 - D0 0 1 Action Unused [7:6] VGATE High Voltage Level = 10.5V VGATE High Voltage Level = 14V VGATE5 PUP polarity active low VGATE5 PUP polarity active high VGATE3 PUP polarity active low VGATE3 PUP polarity active high Channel C PUP polarity active low Channel C PUP polarity active high Channel B PUP polarity active low Channel B PUP polarity active high Channel A PUP polarity active low Channel A PUP polarity active high Summit Microelectronics, Inc 2082 1.7 08/23/04 48 SMH4046 Preliminary Information DEFAULT CONFIGURATION REGISTER SETTINGS - SMH4046FC-232 Register R00 R01 R02 R03 R04 R05 R06 R0C R0D R0E R0F R10 R11 R12 R13 R14 R15 R30 R31 R32 R33 R40 R41 R42 R43 R80 R81 R82 R83 R84 Note 1 R85 R86 R87 R88 R89 R8A R8B Note 1 R8C R8D Note 1 RC1 Contents 0B 9B 80 A0 04 60 0F 4F 3F C7 00 8F 9F AF BF CF DF 0B 92 6A 91 0B AB 94 B2 01 9A 01 9A 0B 35 03 35 01 34 01 34 0A 34 Register R8E R8F R90 R91 R92 R93 R94 R95 R96 R97 R98 R99 R9A R9B R9C R9D R9E R9F RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA8 RA9 RAA RAB RAC RAD RAE RAF RB0 RB1 RB2 RB3 RB4 Contents 02 49 08 67 00 67 09 D7 01 EB 02 23 02 24 0B FF 03 FF 01 0B 00 F6 0B 35 03 FF 00 CE 00 8F 0B 4E 03 9B 0A 67 0A 52 03 Register RB5 RB6 RB7 RB8 RB9 RBA RBB RBC RBD RBE RBF RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RC8 RC9 RCA RCB RCC RCD RCE RCF RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RE0 RE1 RE2 RE3 Contents FF 03 FF 0D 9A 0D 56 0F FF 0F FF 0A 01 09 9A 0B 35 0B FF 0C 00 0C 00 0D FF 0D FF 0C 00 0C 00 0F D8 0F D8 00 3D 00 3D Register RE4 RE5 RE6 RE7 RE8 RE9 REA REB Contents 00 3D 00 3D 00 3D 00 3D Slave Address 1001 R84 Note 1 07 R8B Note 1 00 R8D Note 1 00 The default device ordering number is SMH4046FC-232. It is programmed with the register contents as shown above and tested over the commercial temperature range. New device suffix numbers are assigned to non-default requirements. Note 1 - Two sets of configuration registers R84, R8B and R8D are at different slave addresses, address space 1001 and programmable slave address space 101X. The contents shown on the left side of the table are for address 101X. On the right side at slave address 1001, the contents are 07, 00 and 00. Summit Microelectronics, Inc 2082 1.7 08/23/04 49 SMH4046 Preliminary Information PACKAGE 48 PIN TQ FP PACKAGE 0.354 (9.00) 0.276 (7.00) BSC (A) BSC (B) Inches (Millimeters) 0.02 (0.5) BSC 0.007 - 0.011 (0.17 - 0.27) DETAIL "A" (B) (A) Ref Jedec M S-026 0.037 - 0.041 0.95 - 1.05 Pin 1 Indicator 0.039 (1.00) Ref 0.047 MAX. (1.2) 0 o Min to 7 o Max A B 0.002 - 0.006 (0.05-0.15) 0.018 - 0.030 (0.45 - 0.75) DETAIL "B" Summit Microelectronics, Inc 2082 1.7 08/23/04 50 SMH4046 Preliminary Information PART MARKING SUMMIT SMH4046F Annn Pin 1 Identifier Summit Part Number xx Status Tracking Code (Blank, MS, ES, 01, 02,...) (Summit Use) AYYWW Date Code (YYWW) Lot tracking code (Summit use) Part Number suffix (Contains Customer specific programming and ordering requirements. The default device ordering number is not marked on the part) Drawing not to scale Product Tracking Code (Summit use) ORDERING INFORMATION SMH4046 Summit Part Number F C nnn Customer specific requirements are contained in the suffix such as Hex code, Hex code revision, etc. Part Number Suffix (see page 47) Package F=48 Lead TQFP Temp Range C=Commercial Blank=Industrial NOTICE NOTE 1 - This is a Preliminary Information data sheet that describes a Summit product currently in pre-production with limited characterization. SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user's specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. Revision 1.7 - This document supersedes all previous versions. Data Sheet updates can be accessed by "right" or "left" mouse clicking on the link: http://www.summitmicro.com/prod_select/summary/SMH4046/SMH4046.htm Device Errata sheets can be accessed by "right" or "left" mouse clicking on the link: http://www.summitmicro.com/errata/SMH4046 (c) Copyright 2004 SUMMIT MICROELECTRONICS, Inc. (R) (R) PROGRAMMABLE ANALOG FOR A DIGITAL WORLDTM PICMG and the PICMG logo are registered trademarks of the PCI Industrial Computers Manufacturers Group TM ADOC is a registered trademark of Summit Microelectronics Inc., I2C is a trademark of Philips Corporation. Summit Microelectronics, Inc 2082 1.7 08/23/04 51 |
Price & Availability of SMH4046FC
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |